South Korea's Samsung Electronics Chairman Lee Jae-rong visited Yokohama, Japan on the same day to inspect the advanced chip packaging laboratory that the company started in September this year. Samsung Electronics plans to invest 40 billion yen in the laboratory within five years from 2024 to jointly develop 3D packaging technology for next-generation low-power AI chips, drawing on the advantages of Japanese semiconductor materials and special equipment companies. The report pointed out that since TSMC's advanced packaging production capacity is full until the end of 2026, Samsung Electronics is stepping up competition for one-stop OEM orders for AI chips by taking advantage of the mass production advantage of next-generation high-bandwidth memory chips.

South Korea's Samsung Electronics Chairman Lee Jae-rong visited Yokohama, Japan on the same day to inspect the advanced chip packaging laboratory that the company started in September this year. Samsung Electronics plans to invest 40 billion yen in the laboratory within five years from 2024 to jointly develop 3D packaging technology for next-generation low-power AI chips, drawing on the advantages of Japanese semiconductor materials and special equipment companies. The report pointed out that since TSMC's advanced packaging production capacity is full until the end of 2026, Samsung Electronics is stepping up competition for one-stop OEM orders for AI chips by taking advantage of the mass production advantage of next-generation high-bandwidth memory chips.