Atomera to present 4F² DRAM transistor paper at SISPAD 2026

• Atomera will present DRAM scaling work at SISPAD 2026 in Kumamoto, Japan on Sept. 28, 2026.
• The paper outlines TCAD results supporting 4F² DRAM junctionless vertical-channel transistors using MST-defined substrate doping to meet drive and retention targets.
• A separate SISPAD 2026 poster on Sept. 29, 2026 will cover compact modeling of off-state leakage and breakdown in GaN-on-Si HEMTs.
• The poster compares conventional silicon, high-resistivity silicon, and MST-modified silicon, showing lower low-voltage leakage and delayed high-field current rise with MST.

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