CITIC Securities: Tao's Law Moves Towards Product Verification and Focuses on Logical Folding Industry Chain Opportunities

The Zhitong Finance App learned that CITIC Securities released a research report stating that the Tao Law has moved from a theoretical framework to a product stage. On September 4, He Tingbo, the head of Huawei Semiconductors, published a follow-up paper on Tao Ding, focusing on the power consumption and cooling issues of 3D stacked chips; on September 7, Huawei released the Mate XT2 ULTIMATE DESIGN, which was first equipped with the Kirin 9050 Pro, which improved overall performance by more than 42% compared to the previous generation. The bank believes that the Kirin 9050 Pro has become Tao Dinglu's first product verification window. LogicFolding will increase the demand for multi-layer active wafer manufacturing and wafer-level hybrid bonding, and drive upgrades in CMP, cleaning, deposition, etching, measurement and testing processes. It is recommended to focus on the domestic wafer manufacturing, semiconductor equipment and testing industry chain.

CITIC Securities's main views are as follows:

Incident: Huawei released a follow-up paper on Tao's Law and the Mate XT2 equipped with Kirin 9050 Pro. On September 4, He Tingbo, the head of Huawei Semiconductors, published the paper “Was HUAWEI's Chip Degraded to Melt?” This is the third time in less than four months that a paper has been published or updated on Tao's law after the May 25 and July 3 editions. This time, the focus is on addressing the power consumption and heat dissipation issues of 3D stacked chips. On September 7, Huawei released the Mate XT2 ULTIMATE DESIGN, which was initially equipped with the Kirin 9050 Pro, which improved overall performance by more than 42% compared to the Mate XTS. The bank believes that Tao's law has moved from theoretical verification to the terminal product stage.

The September paper further explained the underlying mechanism of logical folding to improve power consumption and heat dissipation.

The paper points out that dynamic power consumption in typical smartphone workloads accounts for about 90% of total power consumption. In addition to transistor switches, signal transmission in metal connections is also the main source of energy consumption. Logical folding transforms a long-distance horizontal interconnect into a short-distance vertical interconnect. The folding path length of a typical core is reduced by about 20%, and some critical paths are shortened by up to 70%, thereby reducing interconnect capacitance and dynamic power consumption. In the same performance mode, Kirin 2026's NPU, GPU, and CPU performance core power consumption decreased by 66%, 58%, and 41%, respectively, compared to the previous generation. At the same time, transistor density increased by 55%. Preliminary verification that logic folding can balance transistor density and energy efficiency improvements.

The overall performance of the Kirin 9050 Pro has been improved, and it has become an important product verification window for Tao Law.

According to the Huawei press conference, the Kirin 9050 Pro is equipped with a nine-core Lingsai CPU, which increases single-core peak performance by more than 24% and 52%, respectively; the computing unit and cache capacity of Ma Liang's GPU doubled, and rendering performance increased by more than 142%; and the Da Vinci architecture NPU supports a large end-side MoE model with a total parameter of 30B and an activation parameter of 2b. At the same time, the Mate XT2's large file opening speed, multitasking fluency, and 4K video export speed were increased by more than 50%, 35%, and 40%, respectively. The bank believes that the multi-core parallel CPU, the expansion of GPU computing units, and the implementation of large models on the end side are in line with the direction of Tao's law to reduce task time by increasing the degree of parallelism.

The chip package and the cooling of the whole machine were upgraded in collaboration, and the product side initially responded to the 3D stacked cooling problem.

The Kirin 9050 Pro uses a multi-channel thermal conductivity package, and the entire Mate XT2 uses an oversized VC and graphene cross-axis cooling system. Together, the two reduce the game temperature rise by 2.5℃. The paper proposed controlling power density and local hot spots by reducing interconnection power consumption, selective folding, interlaced layout of heating and cooling modules, and thermal sensing design. The bank believes that the chip measurement data in the paper echoes the improved heat dissipation of the whole machine revealed by the new product, and that the verification of Tao's law is being further extended from transistor density and performance to power consumption and heat dissipation.

Hybrid bonding continues to shrink, which is expected to increase the value of wafer manufacturing and equipment.

According to the paper, Kirin 2026's hybrid bonding spacing has reached 1.5 μm, and the number of vertical interconnects has reached 50 million; Kirin 2027 has been further reduced to 1 μm, with more than 100 million vertical interconnects. The target for the next three years will advance to 720 nm and more than 200 million interconnects, pointing at 480 nm for the long term. With the gradual implementation of LogicFolding, the bank anticipates that multi-layer active wafer input and wafer-level hybrid bonding processes are expected to increase, leading to an increase in demand for CMP, cleaning, deposition, etching, alignment, measurement and multi-stage testing.

Risk factors: Demand for downstream AI and terminals fell short of expectations; production expansion and domestic substitution processes in mainland fabs fell short of expectations; increased competition due to expansion; increased geopolitical and trade frictions.

Investment strategy: Focus on the wafer manufacturing, semiconductor equipment and testing industry chains. The bank's subsequent recommendations focus on the measured performance and power consumption performance of the Kirin 9050 Pro, as well as the industrialization progress of LogicFolding and wafer-level hybrid bonding.