Cathay Pacific Haitong: Domestic computing power chips have entered a golden period of development, domestic advanced packaging, testing capacity is in short supply

The Zhitong Finance App learned that in the AI era, Cathay Pacific Haitong released a research report saying that in the AI era, advanced packaging requirements brought about by larger storage capacity, faster inter-chip interconnection bandwidth, and more complex testing requirements, the bank believes that domestic advanced packaging and testing capacity also needs to develop rapidly to meet growing domestic demand. Recently, relevant domestic packaging and testing manufacturers have intensively announced investment plans to expand production. The bank believes that with the continuous development of domestic computing power chips and supernodes, domestic advanced packaging and testing production capacity also needs to be expanded to meet the growing advanced packaging and testing needs of domestic computing power chip design companies.

Cathay Pacific Haitong's main views are as follows:

With larger storage capacity and faster inter-chip interconnection bandwidth, the importance of advanced packaging is becoming more and more important

In the era of large models, hardware equipment needs to be examined from a cluster perspective, because large model training requires both high computing power, large storage capacity and efficient interconnection, and chip storage and inter-chip interconnection bandwidth have become the most important technical indicators. Currently, the industry has two methods for providing chip storage capacity. On the one hand, more advanced technology is used to increase transistor density, and on the other hand, 3D packaging is used to attach the storage to the chip to increase the storage area. There have been many new discussions recently about ways to increase bandwidth, such as making the storage and computing modules closer to shorten the transmission distance, or adopting an architecture that integrates calculation and storage by changing the way the storage is arranged.

AI chip testing faces testing challenges approaching physical limits

The AI computing platform creates a collaborative architecture for task optimization through heterogeneous integration of CPU control units, GPU/NPU accelerators, and DPU data processors, etc., which poses a greater challenge to chip testing. To support the continuous innovation of the AI chip revolution, the test and measurement industry needs to face technical difficulties with ultra-high speed interfaces, heterogeneous system integration complexity, optoelectronic fusion, and system-level testing for AI computing clusters.

Advanced packaging and testing capacity are in short supply, and prices are rising

The AI investment cycle is accelerating the industry towards the “Foundry 2.0” era. Its core feature is the deep integration of wafer manufacturing, advanced packaging, and testing capabilities. In the context of semiconductor giants such as TSMC and Samsung Electronics continuing to increase production capacity, advanced packaging technology represented by CoWoS still has a supply and demand gap of about 10%. In the advanced packaging process, citing MoneyDJ reports, Sun Moon Light will increase the price of various advanced packaging technologies, including CowOS\ FOCos, by up to 20%. The price increase first reflects the rise in raw material prices, and secondly, the increase in capital expenditure, that is, investment cost considerations. In the OEM testing process, citing the Financial Federation, as early as April 1, 2026, due to tight demand for production capacity for some tests, in order to ensure stable and reliable product delivery, Liyang Chip raised the price of a small number of testing services by 10%-15%.

Risk warning: Production expansion progress in advanced packaging/testing plants fell short of expectations; delays in the emergence of popular AI applications made it impossible to achieve a positive cycle of ROI and capital expenditure; bottlenecks in the development of advanced packaging/testing technology caused packaging/testing requirements for AI computing power chips to not be met; more new entrants led to a deterioration in the industry pattern.