Recently, Zhou Peng/Bao Wenzhong's team from Fudan University and Shaoxin Laboratory successfully developed the world's first 32-bit RISC-V architecture microprocessor “stepless” based on two-dimensional semiconductor materials, setting the world's largest engineering scale verification record for two-dimensional chips. The relevant results have been published in the international journal “Nature”. It is worth noting that the results released by the Fudan University team broke through the bottleneck of two-dimensional semiconductor electronics engineering and achieved the integration of 5,900 transistors for the first time. According to information, the “stepless” microprocessor is based on single-layer molybdenum disulfide two-dimensional semiconductor materials, does not rely on advanced EUV lithographers, uses a self-developed characteristic integrated process, and relies on an open source simplified instruction set calculation architecture to achieve independent research and development of the entire chain from materials and architecture to flow sheets. The degree of optimization of the integrated process and large-scale circuit verification results all reached the best level of the same period in the world.

Recently, Zhou Peng/Bao Wenzhong's team from Fudan University and Shaoxin Laboratory successfully developed the world's first 32-bit RISC-V architecture microprocessor “stepless” based on two-dimensional semiconductor materials, setting the world's largest engineering scale verification record for two-dimensional chips. The relevant results have been published in the international journal “Nature”. It is worth noting that the results released by the Fudan University team broke through the bottleneck of two-dimensional semiconductor electronics engineering and achieved the integration of 5,900 transistors for the first time. According to information, the “stepless” microprocessor is based on single-layer molybdenum disulfide two-dimensional semiconductor materials, does not rely on advanced EUV lithographers, uses a self-developed characteristic integrated process, and relies on an open source simplified instruction set calculation architecture to achieve independent research and development of the entire chain from materials and architecture to flow sheets. The degree of optimization of the integrated process and large-scale circuit verification results all reached the best level of the same period in the world.