The Zhitong Finance App learned that CITIC Construction Investment released a research report saying that compared to the development path of advanced packaging processes around the world, the advanced packaging process in mainland China is currently at a stage where the penetration rate of CoWoS technology is rapidly increasing. Since wafer foundries in mainland China have yet to mass-produce mid-stage processes such as RDL, OSAT manufacturers have a presence in the 2.5D/3D/COWOS field. The bank believes that OSAT manufacturers that can take the lead in breaking through mass production and complete capacity expansion are expected to form a first-mover advantage and occupy a high share of the industry. However, as industry trends evolve, the importance of wafer foundries in mainland China in the field of advanced packaging cannot be ignored. Foundry's advantages in cutting-edge technology and equipment production capacity can help it catch up or even surpass in the iteration of advanced packaging technology.
CITIC Construction Investment's main views are as follows:
As an important means of improving chip performance in the post-Moore era, advanced packaging is the main driving force and core increment for the development of the packaging and testing industry
The global advanced packaging scale grew from US$25.29 billion in 2019 to US$40.76 billion in 2024, and is expected to reach US$67.44 billion in 2029. The CAGR from 2024 to 2029 is 10.6%, which is significantly higher than traditional packaging. The advanced packaging market in mainland China also maintained rapid growth. The scale increased from 51.35 billion yuan in 2024 to 100.59 billion yuan in 2029. The CAGR was about 14.4%, and the market share continued to increase. Among them, 2.5D/3D growth is the most prominent. The global scale is expected to increase from US$8.18 billion in 2024 to US$25.82 billion in 2029, with a CAGR of 25.8%.
The driving force of advanced packaging has gradually switched from smart terminals to high-computing power applications such as AI and HPC
With the increase in chip computing power, the number of I/Os has rapidly grown from tens to hundreds to tens of thousands. Traditional packaging is difficult to meet high-density interconnection requirements, driving the evolution of packages to Chiplets and 2.5D/3D heterogeneous integration; at the same time, HBM is developing from flat to high-rise 3D stacking, further increasing the packaging process requirements. In terms of optical interconnection, COUPE is driving the optoelectronic conversion process down to the package layer, forming a growth pattern where computing power, storage, and optical interconnection are cooperatively driven. The importance of advanced packaging in improving chip performance continues to increase.
Currently, a pattern of parallel evolution of multiple technology routes such as CoWoP, CoPOS, SoIC, and EMIB has been formed based on CoWoS
CowOS has entered mass production and is widely used in AI chips, HPC, and HBM; CoBOP reduces costs by replacing traditional carrier boards, CoPOS increases unit output through large panels, and SoIC further increases interconnection density, reduces latency and power consumption through smaller bonding spacing; at the same time, HBM continues to develop towards higher layer stacking, and COUPE promotes the integration of silicon light and advanced packaging. With rapid growth on the demand side, the supply of advanced packaging continues to be tight.
Risk warning: Risk of advanced packaging demand falling short of expectations, risk of technology iteration and route changes, risk of customer introduction and mass production progress, risk of capacity expansion and profitability, risk of supply chain and manufacturing yield.